Because of the power dissipation requirements for power integrated circuits, the power electronics industry currently uses chip packages that do not conform to IC industry standards. Packages designed for surface mounting on printed circuit boards (PCBs) typically include large external rectangular contact pads that are usually formed from copper tungsten alloy or other similar conductive material to match the coefficient of expansion (CTE) of the alumina within the package.
The CTE of the copper/tungsten used in such pads does not accurately match the CTE of the printed circuit board. Consequently, solder fatigue of the pad/PCB joint is a significant problem in assembly and operation of a power switch, and the integrated circuit industry has developed no standard way to solve it. The problem is relatively small for low-power ICs, for which other solutions have been developed, but it much more serious for power switches with their higher operating temperatures and larger component sizes.
The IC industry has introduced PGAs (pin grid arrays) that allow for smaller footprints but does not directly solve the problem of solder fatigue. More recently, ICs that incorporate a ball grid array (BGA) do directly attack the solder fatigue problem between the package and board material by matching the CTE of the array more closely with that of the PCB.
Ceramic packaging technology is traditionally used to support high performance IC devices owing to the high reliability, thermal conductivity and excellent routability of ceramics. The material has a comparatively close coefficient of expansion (CTE) with silicon. Although the thermal conductivity characteristics of ceramic is an advantage for first-level interconnect, they present a problem for second-level mounting on the PCB for power devices.
A power device passes current from the bottom of the device to the top; therefore the die attach pad must be accessible to the outside of the package. Wirebonds are customarily used to direct the current from the top of the die to another pad accessible to the outside of the package, but wirebonding entails the use of resistive junctions between the wire and the pads at either end. Current passing through a resistive junction creates heat. In a power device, elevated resistance in a wirebond junction reduces the current, thereby limiting the power output, and exposes the device to a higher risk of failure from overheating resulting from inadequate dissipation of the heat being generated.
U.S. Pat. No. 5,406,120 to Jones describes a hermetically-sealed semiconductor ceramic package using a large heat dissipating plane brazed to a ceramic substrate, a wirebond method of making electrical connections to the die, a via method of connection through the hermetic seal, and the use of ceramic sidewalls for the hermetic package. The vias in Jones contain copper or other superior conductor plated with silver to facilitate conductive connection; the inner surfaces of the vias are metallized with a refractory metal. The resulting package is complex in its construction and nonstandard in its overall form and PCB mounting, illustrating clearly the problems faced in mounting power devices simply and reliably on PCBs.
U.S. Pat. No. 5,726,493 to Yamashita et al. disclose a ball grid array structure for a semiconductor device in which the device is sealed with a sealing resin and an electrically conductive pin passing through the resin to serve as an electrode member.
U.S. Pat. No. 5,834,839 to Mertol describes a semiconductor package that includes solder balls and an encapsulant covering the semiconductor die and bond wires and forming a protruberance from the lower surface of the package substrate.
U.S. Pat. No. 5,909,058 to Yano et al. describes a semiconductor package and semiconductor mounting part that is focused principally on increasing the number of terminals and decreasing the package size for non-power ICs.
It would be desirable to extend a ball grid array (BGA) connection structure, which is advantageous for integrated circuits, to the attachment of power semiconductor devices to printed circuit boards. This benefit is realized by the present invention.